FPGA (Field Programmable Logic Gate Array) has high flexibility and is an ideal choice for various applications such as smart network cards and telecommunications networks. AMD (formerly Xilinx) released the latest Versal FPGAs on the 27th, which are designed to be simulated and tested before the chip is built.
Rob Bauer, Senior Product Line Manager of the AMD Versal series, pointed out that through these FPGAs, chip designers can create digital twins or digital versions for upcoming ASICs or SOC before the chip is taken out, which helps designers verify and start software development earlier.
Bauer pointed out that as advanced packaging technology transitions to 2.5D and 3D chip architectures, this will only become more difficult for chip manufacturers. Chip designers no longer validate and develop software for single chip devices, but for multi chip devices.
This is also AMD’s positioning for its Versal Premium VP1902. This chip has a size of approximately 77 × 77mm, with 18.5 million logical units, twice the size of the upcoming VU19P, and a dedicated Arm core for controlling flat operations, as well as an onboard network to assist in debugging.
AMD VP1902 is scheduled to provide samples to customers in the third quarter and will be fully available in early 2024.
However, simulating modern SoCs with billions of transistors is quite resource intensive. AMD stated that depending on chip size and complexity, it may need to span multiple racks, tens, or even hundreds of FPGAs.
Although AMD’s latest FPGA is mainly targeted at chip manufacturers, AMD stated that these chips are also very suitable for companies engaged in firmware development and testing, IP block and subsystem prototype development, peripheral verification, and other test cases.
As for compatibility, the new chip will utilize the same underlying Vivado ML software development kit as FPGA. AMD said that it would cooperate with leading EDA suppliers such as Cadence, Siemens and Synopsys to increase support for more advanced functions.
